//功能：Avalon-ST视频流接口的ILI9488驱动模块
module vip_ILI9488(
	input         clk,
	input         clk12p5M,                      
	input         rst_n,
	//Avalon-ST Sink
    input         sink_sop,
    input         sink_valid,
    input  [15:0] sink_data,
    input         sink_eop,
    output        sink_ready,
    //Conduit
    output        lcd_intdone,
	//TFTLCD interface
	output        WR,
	output        RD,
	output        CS,
	output        RS,
	output        BL_cnt,
	output [15:0] data,
	output        RESET
);
wire sop_w0,eop_w0,valid_w0,ready_w0;
wire [15:0] data_w0;
wire        sop_w1;
wire [15:0] data_w1;
wire fifo_empty_w,fifo_rd_w;
wire [7:0] wrusedw_w;
wire pixelReady;
reg  valid_r1;
assign fifo_rd_w = !fifo_empty_w && pixelReady;
assign sink_ready = (wrusedw_w <= 8'd200);
always@(posedge clk12p5M or negedge rst_n)
begin
if(rst_n == 1'b0)
    begin
    valid_r1 <= 1'b0;
    end
else
    begin
    valid_r1 <= fifo_rd_w;
    end
end
vip_ili9488_dcfifo u_vip_ili9488_dcfifo_0 (
	.aclr(!rst_n),
	.data({sink_sop,sink_data}),
	.rdclk(clk12p5M),
	.rdreq(fifo_rd_w),
	.wrclk(clk),
	.wrreq(sink_valid),
	.q({sop_w1,data_w1}),
	.rdempty(fifo_empty_w),
	.wrusedw(wrusedw_w)
	);
ILI9488 u_ILI9488_0(
	.clk12p5M(clk12p5M),                      
	.rst_n(rst_n),
	.x_start(10'd0),//横坐标
	.x_end(10'd479),
	.y_start(10'd0),
	.y_end(10'd319),//纵坐标
	.color(data_w1),      //RGB565
	.sop(sop_w1),
	.write_en(valid_r1),   //high active
	.write_ready(pixelReady),//write_en拉高后必须等待write_ready为高才表示
	.lcd_intdone(lcd_intdone),//TFTLCD 初始化完成标志，高有效
	.WR(WR),
	.RD(RD),
	.CS(CS),
	.RS(RS),
	.BL_cnt(BL_cnt),
	.data(data),
	.RESET(RESET)
	);
endmodule 